1. Field of the Invention
The present invention relates to integrated circuits, and, in particular, to high-density programmable logic devices, such as field programmable gate arrays.
2. Description of the Related Art
In the past, high-density programmable logic devices (PLDs) have been divided into two types: field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). Since the logic cells that are typically used as the building blocks for each of these two types of devices are different, the devices tend to be more suitable for different types of applications. FPGAs generally have logic cells with a small number of inputs, such as discrete gates, multiplexers, and/or look-up tables (LUTs). As such, FPGAs are typically well suited for implementing datapath logic and random logic. For FPGAs that have LUTs as the basic building block, random access memory (RAM) is typically used to create the LUTs. If the LUTs are not being used to create logic functions, these RAM cells can be used to create large RAM structures.
CPLDs, on the other hand, generally have logic cells that have more inputs than FPGA logic cells. For example, CPLD logic cells may be based on programmed array logic (PAL) using AND-OR planes. Like FPGAs, CPLDs are typically well suited for implementing random logic, but CPLDs are also well suited for implementing logic circuits that require a large number of inputs, such as decoders and state machines. On the other hand, CPLDs are not well suited for implementing datapath logic.
A typical decoder receives many inputs and generates a single valid output signal (e.g., high) for only one particular combination of inputs. Because many conventional FPGAs are based on logic cells having relatively few inputs (e.g., LUTs with 4 inputs each), such FPGAs are not well suited for implementing circuits like decoders and state machines that require large numbers of inputs. For example, implementing a relatively simple 10-input decoder in a conventional LUT-based FPGA would require at least three 4-input LUTs configured in two different stages. The speed of such a two-stage decoder would be prohibitively slow for many applications.